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A Practical Guide for SystemVerilog Assertions, by Srikanth Vijayaraghavan, Meyyappan Ramanathan
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SystemVerilog language consists of three categories of features -- Design, Assertions and Testbench. Assertions add a whole new dimension to the ASIC verification process. Engineers are used to writing testbenches in verilog that help verify their design. Verilog is a procedural language and is very limited in capabilities to handle the complex ASICs built today. SystemVerilog assertions (SVA) is a declarative language. The temporal nature of the language provides excellent control over time and allows mulitple processes to execute simultaneously. This provides the engineers a very strong tool to solve their verification problems. The language is still new and the thinking is very different from the user's perspective when compared to standard verilog language. There is not enough expertise or intellectual property available as of today in the field. While the language has been defined very well, there is no practical guide that shows how to use the language to solve real verification problems. This book is a practical guide that will help people to understand this new language and adopt assertion based verification methodology quickly.
- Sales Rank: #2854976 in Books
- Published on: 2005-06-21
- Original language: English
- Number of items: 1
- Dimensions: 9.21" h x .81" w x 6.14" l, 1.65 pounds
- Binding: Hardcover
- 334 pages
Most helpful customer reviews
5 of 5 people found the following review helpful.
good book for beginner, despite minor printing errors
By hummingbird lover
If you're new to Systemverilog's assertion language (SVA), and want to learn the syntax, this book is for you. The book walks through every major SVA construct (sequence, property, implication operator, repetition operators, etc.), providing detailed examples for each construct.
Unfortunately, some examples are difficult to follow. There is a cycle-based signal-diagram for each example, but the diagram is small, unannotated, and ultimately hard to interpret. (You pretty much have to read the text while jumping back and forth to the diagram.)
Also, the book's coverage of methodology is weak. If you're already know how to write SVA constructs, and are more interested in 'when/where/how' to use SVA, then there are better books out there.
3 of 3 people found the following review helpful.
Easy to learn the advanced SVA techniques
By H. Patel
I read VHDLCohen's book for systemverilog assertion but lots of errors in that book. This book is far better for beginners who want to learn how assertion based verification works. It explains SVA with lots of examples.
Really a very good book..
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